1. Field of the Invention
The present invention relates to a method of manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method of manufacturing a crown-shaped DRAM capacitor.
2. Description of the Related Art
A capacitor is a principle component in each dynamic random access memory (DRAM) cell. The amount of electric charges stored in a capacitor can affect its susceptibility to external interference such as alpha particles and hence soft errors. In addition, refreshing frequency also depends on the storage capacity of a capacitor.
A charge storage problem is accentuated by newer generation of memories whose feature dimensions are reduced to below 0.25 .mu.m. To increase the capacitance of a capacitor in a smaller area, effective surface of the capacitor must be increased. The formation of a crown-shaped structure is one of the methods to increase the surface area of a capacitor. To increase capacitance even further, especially for fabricating semiconductor devices having a feature dimension smaller than 0.18 .mu.m, hemispherical silicon grains (HSGs) are also formed on the interior and exterior sidewalls of the crown-shaped structure.
In general, a capacitor with a crown-shaped structure is formed by forming a silicon oxide layer and a silicon nitride layer in sequence over a substrate. A polysilicon plug is next formed through the silicon oxide layer and the silicon nitride layer. A second silicon oxide layer is formed over the silicon nitride layer and the polysilicon plug, and then a crown-shaped opening is formed in the second silicon oxide layer. A doped amorphous silicon layer conformal to the sidewalls of the crown-shaped opening as well as the second silicon oxide layer is formed. Chemical-mechanical polishing (CMP) is next carried out to remove the doped amorphous silicon layer above the second silicon oxide layer so that the lower electrodes of different capacitors are isolated from each other. A portion of the second silicon oxide layer is removed so that an oxide layer with a definite thickness remains on top of the silicon nitride layer as a protective layer. The silicon nitride layer needs to be protected because hemispherical silicon grains (HSGs) may also form over the silicon nitride layer when HSGs are formed over the doped amorphous silicon layer. If a layer of HSGs is formed on the silicon nitride layer, the lower electrode of different capacitor may be short-circuited.
In the aforementioned method, the second silicon oxide layer must be etched twice in two separate etching operations. Since there is no reference etching point layer for determining the end of the operation, the first etching operation can only be arbitrarily controlled by etching duration. In general, the first etching of the second silicon oxide layer is conducted using diluted hydrofluoric acid (DHF) or hydrogen fluoride steam. If diluted hydrofluoric acid is used to carry out the etching, silicon wafers are normally inserted vertically into a bath of the liquid. Consequently, the portion of the wafer dipped into the bath the earliest will remain in the bath for the longest period. Moreover, different portions of the wafer will be immersed inside the bath for a different duration. Hence, the resulting thickness of the second silicon oxide layer on a wafer will vary from place to place, and the capacitance of each capacitor will be different, with serious consequences.
On the other hand, if hydrogen fluoride vapor steam is used to carry out the etching, some non-volatile residues may adhere to the surface of the wafer. These residues are difficult to remove and may lead to the formation of defects on the wafer.